Those skilled in the art understand that integrated circuit dimensions are becoming increasingly smaller. Indeed, there is a desire to produce integrated circuit devices, such as transistors, which exhibit a pitch scaling <100 nm and still further <50 nm. As the pitch scaling continues to decrease, it becomes increasingly more difficult to make electrical contact to transistor source, drain and gate regions from above the transistor (as is commonly done in the prior art). The dimensions of the gate contact, made from above the transistor, may exceed the length dimension of the transistor and extend above the source region and drain region. Such extension can effectively block access to the source and drain regions from above the transistor.
There is accordingly a need in the art for an alternatively means to make electrical contact to transistor source and drain regions in instances of increasingly smaller transistor pitch scaling.